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3.3v 4k/8k/16k/32k x 8/9 dual-port static ram cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-06051 rev. *a revised december 27, 2002 25/0251 features ? true dual-ported memory cells which allow simulta- neous access of the same memory location 4k/8k/16k/32k x 8 organizations (cy7c0138av/144av/006av/007av) 4k/8k/16k/32k x 9 organizations (cy7c0139av/145av/016av/017av) 0.35-micron cmos for optimum speed/power high-speed access: 20/25 ns low operating power ? active: i cc = 115 ma (typical) ? standby: i sb3 = 10 a (typical) fully asynchronous operation automatic power-down expandable data bus to 16/18 bits or more using master/ slave chip select when using more than one device on-chip arbitration logic semaphores included to permit software handshaking between ports int flag for port-to-port communication pin select for master or slave commercial and industrial temperature ranges available in 68-pin plcc (all) and 64-pin tqfp (7c006av & 7c144av) pin-compatible and functionally equivalent to idt70v05, 70v06, and 70v07. notes: 1. i/o 0 ? i/o 7 for x8 devices; i/o 0 ? i/o 8 for x9 devices. 2. a 0 ? a 11 for 4k devices; a 0 ? a 12 for 8k devices; a 0 ? a 13 for 16k devices; a 0 ? a 14 for 32k devices; 3. busy is an output in master mode and an input in slave mode. i/o control address decode a 0l ? a 11 ? 14l ce l oe l r/w l busy l i/o control interrupt semaphore arbitration sem l int l m/s a 0l ? a 11 ? 14l true dual-ported ram array a 0r ? a 11 ? 14r ce r oe r r/w r busy r sem r int r address decode a 0r ? a 11 ? 14r [1] [1] [3] [3] r/w l oe l i/o 0l ? i/o 7/8l ce l r/w r oe r i/o 0r ? i/o 7/8r ce r 12 ? 15 8/9 12 ? 15 8/9 12 ? 15 12 ? 15 [2] [2] [2] [2] logic block diagram for the most recent information, visit the cypress web site at www.cypress.com
cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av document #: 38-06051 rev. *a page 2 of 20 functional description the cy7c138av/144av/006av/007av and cy7c139av/ 145av/ 016av/017av are low-power cmos 4k, 8k, 16k, and 32k x8/9 dual-port static rams. various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. two ports are pro- vided, permitting independent, asynchronous access for reads and writes to any location in memory. the devices can be uti- lized as standalone 8/9-bit dual-port static rams or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static ram. an m/s pin is provid- ed for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. application areas include interpro- cessor/multiprocessor designs, communications status buffer- ing, and dual-port video/graphics memory. each port has independent control pins: chip enable (ce ), read or write enable (r/w ), and output enable (oe ). two flags are provided on each port (busy and int ). busy sig- nals that the port is trying to access the same location currently being accessed by the other port. the interrupt flag (int ) per- mits communication between ports or systems by means of a mail box. the semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphore logic is comprised of eight shared latches. only one side can control the latch (semaphore) at any time. control of a semaphore indicates that a shared re- source is in use. an automatic power-down feature is con- trolled independently on each port by a chip select (ce ) pin. pin configurations notes: 4. i/o 8l on the cy7c139av. 5. i/o 8r on the cy7c139av. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 67 top view 68-pin plcc 60 59 58 57 56 55 54 53 52 51 50 49 48 3132 33 34 35 36 37 38 39 40 41 42 43 5 4 3 2 1 68 66 65 64 63 62 61 a a 4l a 3l a 2l a 1l a 0l int l busy l gnd m/s busy r int r a 0r i/o 2l i/o 3l i/o 4l i/o 5l gnd i/o 6l i/o 7l v cc gnd i/o 0r i/o 1r i/o 2r v cc a 2728 29 30 98 7 6 47 46 45 44 a 1r a 2r a 3r a 4r i/o 3r i/o 4r i/o 5r i/o 6r 25 26 6l 7l a 8l a 9l a a 10l 11l v cc nc nc ce l sem l r/w l oe l nc i/o i/o 1l 0l a a 6r 7r a 8r a 9r a 10r nc nc ce r sem r r/w r oe r i/o 7r gnd a 11r a 5r a 5l nc cy7c138av (4k x 8) [5] [4] nc nc cy7c139av (4k x 9)
cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av document #: 38-06051 rev. *a page 3 of 20 notes: 6. i/o 8l on the cy7c145av. 7. i/o 8r on the cy7c145av. pin configurations (continued) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 67 top view 68-pin plcc 60 59 58 57 56 55 54 53 52 51 50 49 48 3132 33 34 35 36 37 38 39 40 41 42 43 5432168 666564636261 a a 4l a 3l a 2l a 1l a 0l int l busy l gnd m/s busy r int r a 0r i/o 2l i/o 3l i/o 4l i/o 5l gnd i/o 6l i/o 7l v cc gnd i/o 0r i/o 1r i/o 2r v cc a 2728 29 30 98 7 6 47 46 45 44 a 1r a 2r a 3r a 4r i/o 3r i/o 4r i/o 5r i/o 6r 25 26 6l 7l a 8l a 9l a a 10l 11l v cc nc nc ce l sem l r/w l oe l nc i/o i/o 1l 0l a a 6r 7r a 8r a 9r a 10r nc nc ce r sem r r/w r oe r i/o 7r gnd a 11r a 5r a 5l nc a 12l a 12r cy7c144av (8k x 8) [7] [6] cy7c145av (8k x 9) 64-pin tqfp top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 50 32 49 16 gnd oe r i/o 2l i/o 3l i/o 4l i/o 5l i/o 6l i/o 7l v cc gnd i/o 0r i/o 1r i/o 2r i/o 3r i/o 4r i/o 5r i/o 6r gnd v cc a 4l a 3l a 2l a 1l a 0l gnd busy l busy r m/s a 0r a 1r a 2r a 3r a 4r int l int r i/o 7r a 5r a 12r a 11r a 10r a 9r a 8r a 7r a 6r nc ce r sem r r/w r v cc oe l i/o 1l i/o 0l a 5l a 12l a 11l a 10l a 9l a 8l a 7l a 6l nc ce l sem l r/w l cy7c144av (8k x 8)
cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av document #: 38-06051 rev. *a page 4 of 20 notes: 8. i/o for cy7c016av and cy7c017av only. nc for other parts. 9. address line for cy7c007av and cy7c017av only. nc for other parts. pin configurations (continued) top view 68-pin plcc v cc oe l i/o 1l i/o 0l a 12l a 11l a 10l a 9l a 8l a 7l a 6l a 13l ce l sem l r/w l i/o 2l i/o 3l i/o 4l i/o 5l i/o 6l i/o 7l v cc gnd i/o 0r i/o 1r i/o 2r i/o 3r i/o 4r i/o 5r gnd v cc a 4l a 3l a 2l a 1l a 0l gnd busy l busy r m/s a 0r a 1r a 2r a 3r a 4r int l int r gnd oe r i/o 7r a 5r a 12r a 11r a 10r a 9r a 8r a 7r a 6r a 13r ce r sem r r/w r a 5l i/o 8l i/o6 r cy7c006av (16k x 8) 24 25 26 10 11 12 13 14 15 48 47 46 45 44 40 41 27 42 28 43 29 30 31 32 33 68 34 67 35 66 36 65 37 64 38 63 39 62 61 16 59 58 57 56 55 54 53 52 51 50 49 60 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 [8] a 14r [9] a 14l [9] cy7c007av (32k x 8) cy7c016av (16k x 9) cy7c017av (32k x 9) i/o 8r [8] 64-pin tqfp top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 50 32 49 16 gnd oe r i/o 2l i/o 3l i/o 4l i/o 5l i/o 6l i/o 7l v cc gnd i/o 0r i/o 1r i/o 2r i/o 3r i/o 4r i/o 5r i/o 6r gnd v cc a 4l a 3l a 2l a 1l a 0l gnd busy l busy r m/s a 0r a 1r a 2r a 3r a 4r int l int r i/o 7r a 5r a 12r a 11r a 10r a 9r a 8r a 7r a 6r a 13r ce r sem r r/w r v cc oe l i/o 1l i/o 0l a 5l a 12l a 11l a 10l a 9l a 8l a 7l a 6l a 13l ce l sem l r/w l cy7c006av (16k x 8)
cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av document #: 38-06051 rev. *a page 5 of 20 maximum ratings [10] (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied............................................. ? 55 c to +125 c supply voltage to ground potential ............... ? 0.5v to +4.6v dc voltage applied to outputs in high z state ........................... ? 0.5v to v cc +0.5v dc input voltage [11] ................................. ? 0.5v to v cc +0.5v output current into outputs (low)............................. 20 ma static discharge voltage .......................................... >2001v latch-up current.................................................... >200 ma notes: 10. the voltage on any input or i/o pin can not exceed the power pin during power-up. 11. pulse width < 20 ns. 12. industrial parts are available in cy7c007av and cy7c017av only. selection guide cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av -20 cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av -25 maximum access time (ns) 20 25 typical operating current (ma) 120 115 typical standby current for i sb1 (ma) (both ports ttl level) 35 30 typical standby current for i sb3 ( a) (both ports cmos level) 10 a 10 a pin definitions left port right port description ce l ce r chip enable r/w l r/w r read/write enable oe l oe r output enable a 0l ? a 14l a 0r ? a 14r address (a 0 ? a 11 for 4k devices; a 0 ? a 12 for 8k devices; a 0 ? a 13 for 16k devices; a 0 ? a 14 for 32k) i/o 0l ? i/o 8l i/o 0r ? i/o 8r data bus input/output (i/o 0 ? i/o 7 for x8 devices and i/o 0 ? i/o 8 for x9) sem l sem r semaphore enable int l int r interrupt flag busy l busy r busy flag m/s master or slave select v cc power gnd ground nc no connect operating range range ambient temperature v cc commercial 0 c to +70 c 3.3v 300 mv industrial [12] ? 40 c to +85 c 3.3v 300 mv
cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av document #: 38-06051 rev. *a page 6 of 20 notes: 13. f max = 1/t rc . all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3 . 14. tested initially and after any design or process changes that may affect these parameters. electrical characteristics over the operating range parameter description cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av -20 -25 unit min. typ. max. min. typ. max. v oh output high voltage (v cc = 3.3v) 2.4 2.4 v v ol output low voltage 0.4 0.4 v v ih input high voltage 2.0 2.0 v v il input low voltage 0.8 0.8 v i oz output leakage current ? 10 10 ? 10 10 a i cc operating current (v cc = max., i out = 0 ma) outputs disabled com ? l. 120 175 115 165 ma ind. [12] 140 195 ma i sb1 standby current (both ports ttl level) ce l & ce r v ih , f = f max [13] com ? l. 35 45 30 40 ma ind. [12] 45 55 ma i sb2 standby current (one port ttl level) ce l | ce r v ih , f = f max [13] com ? l. 75 110 65 95 ma ind. [12] 85 130 ma i sb3 standby current (both ports cmos level) ce l & ce r v cc ? 0.2v, f = 0 [13] com ? l. 10 500 10 500 a ind. [12] 10 500 a i sb4 standby current (one port cmos level) ce l | ce r v ih , f = f max [13] com ? l. 70 95 60 80 ma ind. [12] 80 105 ma capacitance [14] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 10 pf c out output capacitance 10 pf ac test loads and waveforms 3.0v gnd 90% 90% 10% 3ns 3 ns 10% all input pulses (a) normal load (load 1) r1 = 590 ? 3.3v output r2 = 435 ? c= 30 pf v th =1.4v output c = 30 pf (b) th veninequivalent (load 1) (c) three-state delay (load 2) r1 = 590 ? r2 = 435 ? 3.3v output c= 5pf r th = 250 ? including scope and jig) (used for t lz , t hz , t hzwe & t lzwe
cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av document #: 38-06051 rev. *a page 7 of 20 switching characteristics over the operating range [15] parameter description cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av unit -20 -25 min. max. min. max. read cycle t rc read cycle time 20 25 ns t aa address to data valid 20 25 ns t oha output hold from address change 3 3 ns t ace [16] ce low to data valid 20 25 ns t doe oe low to data valid 12 13 ns t lzoe [17, 18, 19] oe low to low z 3 3 ns t hzoe [17, 18, 19] oe high to high z 12 15 ns t lzce [17, 18, 19] ce low to low z 3 3 ns t hzce [17, 18, 19] ce high to high z 12 15 ns t pu [19] ce low to power-up 0 0 ns t pd [19] ce high to power-down 20 25 ns write cycle t wc write cycle time 20 25 ns t sce [16] ce low to write end 16 20 ns t aw address valid to write end 16 20 ns t ha address hold from write end 0 0 ns t sa [16] address set-up to write start 0 0 ns t pwe write pulse width 16 20 ns t sd data set-up to write end 12 15 ns t hd data hold from write end 0 0 ns t hzwe [18, 19] r/w low to high z 12 15 ns t lzwe [18, 19] r/w high to low z 3 3 ns t wdd [20] write pulse to data delay 40 50 ns t ddd [20] write data valid to read data valid 30 35 ns busy timing [21] t bla busy low from address match 20 20 ns t bha busy high from address mismatch 20 20 ns t blc busy low from ce low 20 20 ns t bhc busy high from ce high 16 17 ns t ps port set-up for priority 5 5 ns note: 15. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v, and output loading of the specified i oi /i oh and 30-pf load capacitance. 16. to access ram, ce =l, sem =h. to access semaphore, ce =h and sem =l. either condition must be valid for the entire t sce time. 17. at any given temperature and voltage condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 18. test conditions used are load 3. 19. this parameter is guaranteed but not tested. for information on port-to-port delay through ram cells from writing port to re ading port, refer to read timing with busy waveform. 20. for information on port-to-port delay through ram cells from writing port to reading port, refer to read timing with busy wa veform. 21. test conditions used are load 2.
cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av document #: 38-06051 rev. *a page 8 of 20 data retention mode the cy7c0138av/144av/006av/007av and cy7c139av/ 145av/016av/017av are designed with battery backup in mind. data retention voltage and supply current are guaran- teed over temperature. the following rules ensure data reten- tion: 1. chip enable (ce ) must be held high during data retention, with- in v cc to v cc ? 0.2v. 2. ce must be kept between v cc ? 0.2v and 70% of v cc during the power-up and power-down transitions. 3. the ram can begin operation >t rc after v cc reaches the minimum operating voltage (3.0 volts). notes: 22. t bdd is a calculated parameter and is the greater of t wdd ? t pwe (actual) or t ddd ? t sd (actual). 23. ce = v cc , v in = gnd to v cc , t a = 25 c. this parameter is guaranteed but not tested. t wb r/w high after busy (slave) 0 0 ns t wh r/w high after busy high (slave) 15 17 ns t bdd [22] busy high to data valid 20 25 ns interrupt timing [21] t ins int set time 20 20 ns t inr int reset time 20 20 ns semaphore timing t sop sem flag update pulse (oe or sem ) 10 12 ns t swrd sem flag write to read time 5 5 ns t sps sem flag contention window 5 5 ns t saa sem address access time 20 25 ns switching characteristics over the operating range [15] (continued) parameter description cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av unit -20 -25 min. max. min. max. timing parameter test conditions [23] max. unit icc dr1 @ vcc dr = 2v 50 a data retention mode 3.0v 3.0v v cc > 2.0v v cc to v cc ? 0.2v v cc ce t rc v ih
cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av document #: 38-06051 rev. *a page 9 of 20 switching waveforms notes: 24. r/w is high for read cycles. 25. device is continuously selected ce = v il . this waveform cannot be used for semaphore reads. 26. oe = v il . 27. address valid prior to or coincident with ce transition low. 28. to access ram, ce = v il , sem = v ih . to access semaphore, ce = v ih , sem = v il . t rc t aa t oha data valid previous data valid data out address t oha read cycle no. 1 (either port address access) [24, 25, 26] t ace t lzoe t doe t hzoe t hzce data valid t lzce t pu t pd i sb i cc data out oe ce current read cycle no. 2 (either port ce /oe access) [24, 27, 28] data out t rc address t aa t oha ce t lzce t abe t hzce t ace t lzce read cycle no. 3 (either port) [24, 26, 27, 28]
cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av document #: 38-06051 rev. *a page 10 of 20 notes: 29. r/w must be high during all address transitions. 30. a write occurs during the overlap (t sce or t pwe ) of a low ce or sem . 31. t ha is measured from the earlier of ce or r/w or (sem or r/w ) going high at the end of write cycle. 32. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t pwe or (t hzwe + t sd ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t sd . if oe is high during an r/w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t pwe . 33. transition is measured 500 mv from steady state with a 5-pf load (including scope and jig). this parameter is sampled and not 100% tested. 34. to access ram, ce = v il , sem = v ih . 35. during this period, the i/o pins are in the output state, and input signals must not be applied. 36. if the ce or sem low transition occurs simultaneously with or after the r/w low transition, the outputs remain in the high-impedance state. switching waveforms (continued) t aw t wc t pwe t hd t sd t ha ce r/w oe data out data in address t hzoe t sa t hzwe t lzwe write cycle no. 1: r/w controlled timing [29, 30, 31, 32] [33] [33] [32] [34] [35] [35] t aw t wc t sce t hd t sd t ha ce r/w data in address t sa write cycle no. 2: ce controlled timing [29, 30, 31, 36] [34]
cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av document #: 38-06051 rev. *a page 11 of 20 notes: 37. ce = high for the duration of the above timing (both write and read cycle). 38. i/o 0r = i/o 0l = low (request semaphore); ce r = ce l = high. 39. semaphores are reset (available to both ports) at cycle start. 40. if t sps is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpr edictable. switching waveforms (continued) t sop t saa valid adress valid adress t hd data in valid data out valid t oha t aw t ha t ace t sop t sce t sd t sa t pwe t swrd t doe write cycle read cycle oe r/w i/o 0 sem a 0 ? a 2 semaphore read after write timing, either side [37] match t sps a 0l ? a 2l match r/w l sem l a 0r ? a 2r r/w r sem r timing diagram of semaphore contention [38, 39, 40]
cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av document #: 38-06051 rev. *a page 12 of 20 note: 41. ce l = ce r = low. switching waveforms (continued) valid t ddd t wdd match match r/w r data in r data outl t wc address r t pwe valid t sd t hd address l t ps t bla t bha t bdd busy l timing diagram of read with busy (m/s =high) [41] t pwe r/w busy t wb t wh write timing with busy input (m/s =low)
cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av document #: 38-06051 rev. *a page 13 of 20 note: 42. if t ps is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side busy will be asserted. switching waveforms (continued) address match t ps t blc t bhc address match t ps t blc t bhc ce r validfirst: address l,r busy r ce l ce r busy l ce r ce l address l,r busy timing diagram no. 1 (ce arbitration) [42] ce l valid first: address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r right address valid first: busy timing diagram no. 2 (address arbitration) [42] left address valid first
cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av document #: 38-06051 rev. *a page 14 of 20 notes: 43. t ha depends on which enable pin (ce l or r/w l ) is deasserted first. 44. t ins or t inr depends on which enable pin (ce l or r/w l ) is asserted last. switching waveforms (continued) interrupt timing diagrams write fff (see functional description) t wc right side clears int r : t ha read fff t rc t inr write ffe (see functional description) t wc right side sets int l : left side sets int r : left side clears int l : read ffe t inr t rc address r ce l r/w l int l oe l address r r/w r ce r int l address r ce r r/w r int r oe r address l r/w l ce l int r t ins t ha t ins (see functional description) (see functional description) [43] [44] [44] [44] [43] [44]
cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av document #: 38-06051 rev. *a page 15 of 20 architecture the cy7c138av/144av/006av/007av and cy7c139av/ 145av/016av/017av consist of an array of 4k, 8k, 16k, and 32k words of 8 and 9 bits each of dual-port ram cells, i/o and address lines, and control signals (ce , oe , r/w ). these control pins permit independent access for reads or writes to any location in memory. to handle simultaneous writes/reads to the same location, a busy pin is provided on each port. two interrupt (int ) pins can be utilized for port-to-port communication. two semaphore (sem ) control pins are used for allocating shared resources. with the m/s pin, the device can function as a master (busy pins are outputs) or as a slave (busy pins are inputs). the device also has an automatic power- down feature controlled by ce . each port is provided with its own output enable control (oe ), which allows data to be read from the device. functional description read and write operations when writing data must be set up for a duration of t sd before the rising edge of r/w in order to guarantee a valid write. a write operation is controlled by either the r/w pin (see write cycle no. 1 waveform) or the ce pin (see write cycle no. 2 waveform). required inputs for non-contention operations are summarized in tab le 1 . if a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; other- wise the data read is not deterministic. data will be valid on the port t ddd after the data is presented on the other port. when reading the device, the user must assert both the oe and ce pins. data will be available t ace after ce or t doe after oe is asserted. if the user wishes to access a semaphore flag, then the sem pin must be asserted instead of the ce pin and oe must also be asserted. interrupts the upper two memory locations may be used for message passing. the highest memory location (fff for the cy7c138av/9av, 1fff for the cy7c144av/5av, 3fff for the cy7c006av/16av, 7fff for the cy7c007av/17av) is the mailbox for the right port and the second-highest memory lo- cation (ffe for the cy7c138av/9av, 1ffe for the cy7c144av/5av, 3ffe for the cy7c006av/16av, 7ffe for the cy7c007av/17av) is the mailbox for the left port. when one port writes to the other port ? s mailbox, an interrupt is gen- erated to the owner. the interrupt is reset when the owner reads the contents of the mailbox. the message is user de- fined. each port can read the other port ? s mailbox without resetting the interrupt. the active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. if an application does not require message passing, do not connect the interrupt pin to the processor ? s interrupt request input pin. the operation of the interrupts and their interaction with busy are summarized in table 2. busy the cy7c138av/144av/006av/007av and cy7c139av/ 145av/016av/017av provide on-chip arbitration to resolve simulta- neous memory location access (contention). if both ports ? ce s are asserted and an address match occurs within t ps of each other, the busy logic will determine which port has access. if t ps is violated, one port will definitely gain permission to the location, but it is not predict- able which port will get that permission. busy will be asserted t bla after an address match or t blc after ce is taken low. master/slave an m/s pin is provided in order to expand the word width by config- uring the device as either a master or a slave. the busy output of the master is connected to the busy input of the slave. this will allow the device to interface to a master device with no external compo- nents. writing to slave devices must be delayed until after the busy input has settled (t blc or t bla ), otherwise, the slave chip may begin a write cycle during a contention situation. when tied high, the m/s pin allows the device to be used as a master and, therefore, the busy line is an output. busy can then be used to send the arbitra- tion outcome to a slave. semaphore operation the cy7c138av/144av/006av/007av and cy7c139av/ 145av/016av/017av provide eight semaphore latches, which are separate from the dual-port memory locations. sema- phores are used to reserve resources that are shared between the two ports. the state of the semaphore indicates that a resource is in use. for example, if the left port wants to request a given resource, it sets a latch by writing a zero to a sema- phore location. the left port then verifies its success in setting the latch by reading it. after writing to the semaphore, sem or oe must be deasserted for t sop before attempting to read the sema- phore. the semaphore value will be available t swrd + t doe after the rising edge of the semaphore write. if the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. when the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. if the left side no longer requires the sema- phore, a one is written to cancel its request. semaphores are accessed by asserting sem low. the sem pin functions as a chip select for the semaphore latches (ce must remain high during sem low). a 0 ? 2 represents the semaphore address. oe and r/w are used in the same manner as a normal memory access. when writing or reading a semaphore, the other address pins have no effect. when writing to the semaphore, only i/o 0 is used. if a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. that semaphore can now only be modified by the side showing zero (the left port in this case). if the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. howev- er, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. table 3 shows sample semaphore operations. when reading a semaphore, all data lines output the sema- phore value. the read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. if both ports attempt to access the sema- phore within t sps of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av document #: 38-06051 rev. *a page 16 of 20 table 1. non-contending read/write inputs outputs ce r/w oe sem i/o 0 ? i/o 8 operation h x x h high z deselected: power-down h h l l data out read data in semaphore flag x x h x high z i/o lines disabled h x l data in write into semaphore flag l h l h data out read l l x h data in write l x x l not allowed table 2. interrupt operation example (assumes busy l =busy r =high) left port right port function r/w l ce l oe l a 0 l ? 14 l int l r/w r ce r oe r a 0r ? 14r int r set right int r flag l l x fff [45] x x x x x l [46] reset right int r flag x x x x x x l l fff [45] h [47] set left int l flag x x x x l [47] l l x 1ffe [45] x reset left int l flag x l l 1ffe [45] h [46] x x x x x table 3. semaphore operation example function i/o 0 ? i/o 8 left i/o 0 ? i/o 8 right status no action 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token right port writes 0 to semaphore 0 1 no change. right side has no write access to semaphore left port writes 1 to semaphore 1 0 right port obtains semaphore token left port writes 0 to semaphore 1 0 no change. left port has no write access to semaphore right port writes 1 to semaphore 0 1 left port obtains semaphore token left port writes 1 to semaphore 1 1 semaphore free right port writes 0 to semaphore 1 0 right port has semaphore token right port writes 1 to semaphore 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token left port writes 1 to semaphore 1 1 semaphore free note: 45. see functional description for specific addresses by device part number. 46. if busy l = l, then no change. 47. if busy r = l, then no change.
cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av document #: 38-06051 rev. *a page 17 of 20 ordering information package availability guide device organization 68-pin plcc 64-pin tqfp cy7c138av 4k x 8 x cy7c139av 4k x 9 x cy7c144av 8k x 8 x x cy7c145av 8k x 9 x cy7c006av 16k x 8 x x cy7c016av 16k x 9 x cy7c007av 32k x 8 x cy7c017av 32k x 9 x 4k x8 3.3v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 20 cy7c138av ? 20jc j81 68-pin plastic leaded chip carrier commercial 25 cy7c138av ? 25jc j81 68-pin plastic leaded chip carrier commercial 4k x9 3.3v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 20 cy7c139av ? 20jc j81 68-pin plastic leaded chip carrier commercial 25 cy7c139av ? 25jc j81 68-pin plastic leaded chip carrier commercial 8k x8 3.3v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 20 cy7c144av ? 20ac a65 64-pin thin quad flat pack commercial cy7c144av ? 20jc j81 68-pin plastic leaded chip carrier 25 cy7c144av ? 25ac a65 64-pin thin quad flat pack commercial cy7c144av ? 25jc j81 68-pin plastic leaded chip carrier 8k x9 3.3v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 20 cy7c145av ? 20jc j81 68-pin plastic leaded chip carrier commercial 25 cy7c145av ? 25jc j81 68-pin plastic leaded chip carrier commercial 16k x8 3.3v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 20 cy7c006av ? 20ac a65 64-pin thin quad flat pack commercial cy7c006av ? 20jc j81 68-pin plastic leaded chip carrier 25 cy7c006av ? 25ac a65 64-pin thin quad flat pack commercial cy7c006av ? 25jc j81 68-pin plastic leaded chip carrier
cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av document #: 38-06051 rev. *a page 18 of 20 ordering information (continued) 16k x9 3.3v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 20 cy7c016av ? 20jc j81 68-pin plastic leaded chip carrier commercial 25 cy7c016av ? 25jc j81 68-pin plastic leaded chip carrier commercial 32k x8 3.3v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 20 cy7c007av ? 20jc j81 68-pin plastic leaded chip carrier commercial cy7c007av ? 20ji j81 68-pin plastic leaded chip carrier industrial 25 cy7c007av ? 25jc j81 68-pin plastic leaded chip carrier commercial 32k x9 3.3v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 20 cy7c017av ? 20jc j81 68-pin plastic leaded chip carrier commercial cy7c017av ? 20ji j81 68-pin plastic leaded chip carrier industrial 25 cy7c017av ? 25jc j81 68-pin plastic leaded chip carrier commercial
cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av document #: 38-06051 rev. *a page 19 of 20 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagrams 64-lead thin plastic quad flat pack (14 x 14 x 1.4 mm) a65 51-85046-b 68-lead plastic leaded chip carrier j81 51-85005-a
cy7c138av/144av/006av cy7c139av/145av/016av cy7c007av/017av document #: 38-06051 rev. *a page 20 of 20 document title: cy7c138av/144av/006av/cy7c139av/145av/016av/cy7c007av/017av 3.3v 4k/8k/16k/32k x 8/9 dual port sram document number: 38-06051 rev. ecn no. issue date orig. of change description of change ** 110203 12/02/01 szv change from spec number: 38-00837 to 38-06051 *a 122301 12/27/02 rbi power up requirements added to maximum ratings information

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